It is desired to form integrated circuitry to ever-higher levels of integration. Capacitors are commonly utilized in integrated circuitry, and it is desired to shrink capacitors to ever-tighter lateral dimensions in order to conserve valuable semiconductor real estate.
One type of capacitor is a so-called container device. A storage electrode (i.e., storage node) of such device is shaped as a container. Dielectric material and another capacitor electrode (i.e., plate electrode) may be formed within the container and along an outer edge of the container, which can form a capacitor having high capacitance and a small footprint.
Container-shaped storage nodes are becoming increasingly taller and narrower (i.e., are being formed to higher aspect ratios) in an effort to achieve desired levels of capacitance while decreasing the amount of semiconductor real estate consumed by individual capacitors. Unfortunately, high-aspect-ratio storage nodes can be structurally weak; and subject to toppling, twisting and/or breaking from an underlying base.
Lattice methodology has been developed to avoiding toppling of high-aspect-ratio containers. In such methodology, a lattice is provided to hold container-shaped electrodes from toppling.
Example prior art lattice methodology is described with reference to FIGS. 1-5.
Referring to FIG. 1, a prior art assembly 10 is shown to comprise a pair of adjacent storage nodes 12a and 12b. Each of the storage nodes comprises conductive material 14 configured in an upwardly-opening container shape. Each of the container-shaped storage nodes 12a and 12b has a first side surface 15 and a second side surface 17; with the second side surface 17 being taller than the first side surface 15.
Lattices 18, 20 and 22 are along the second side surfaces 17 of the container-shaped storage nodes 12a and 12b. The lattices comprise lattice material 16 (e.g., silicon nitride).
The lattices 18, 20 and 22 may be referred to as a lower-level lattice, a mid-level lattice and a higher-level lattice, respectively.
The lower-level lattice 18 is supported by an underlying material 24 (e.g., silicon dioxide). Conductive interconnects 26a and 26b extend through the material 24 to connect with the storage nodes 12a and 12b, respectively. The material 24 and the interconnects 26a and 26b may be considered to form a supporting base for the storage nodes 12a and 12b. 
The interconnects 26a and 26b couple the storage nodes 12a and 12b with transistors 28a and 28b, respectively. Each of the transistors 28a and 28b comprises a pair of source/drain regions. One of the source/drain regions of the transistor 28a is coupled with the interconnect 26a and the other is coupled with a bitline BL(a); and one of the source/drain regions of the transistor 28b is coupled with the interconnect 26b and the other is coupled with a bitline BL(b). Each of the transistors 28a and 28b comprises a gate which is coupled with a wordline. The gate of the transistor 28a is coupled with a wordline WL(a), and the gate of the transistor 28b is coupled with a wordline WL(b).
The storage nodes 12a, 12b and the associated transistors 28a, 28b may be incorporated into a memory array (with an example memory array being discussed below with reference to FIG. 4). In such embodiments, the neighboring storage nodes 12a and 12b may both be coupled with a common bitline (i.e., BL(a) and BL(b) may be the same bitline) if the neighboring storage nodes are along a same column as one another, or may both be coupled with a common wordline (i.e., WL(a) and WL(b) may be the same wordline) if the neighboring storage nodes are along a same row as one another.
The various structures of FIG. 1 may be supported by an underlying semiconductor substrate (not shown). The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, a semiconductor substrate.
One aspect of the prior art configuration of FIG. 1 is that the higher-level lattice 22 is patterned identically to the middle-level lattice 20. FIGS. 2A and 2B diagrammatically illustrate such patterning.
FIGS. 2A and 2B show a plurality of storage nodes 12 arranged in a hexagonally-packed pattern. The higher-level lattices 22 are shown in FIG. 2A, and the middle-level lattices 20 are shown in FIG. 2B. One of the higher-level lattices 22 of FIG. 2A is labeled as a lattice 22a so that it may be specifically identified, and is surrounded with a box 30; and one of the middle-levels lattices 20 of FIG. 2B is labeled as a lattice 20a so that it may be specifically identified, and is surrounded with the box 32. The higher-level lattice 22a is associated with the same storage nodes 12 as the middle-level lattice 20a, and is directly over the middle-level lattice 20a. 
The storage nodes 12a and 12b may be incorporated into capacitors, as shown in FIG. 3. Specifically, capacitor dielectric material 34 is provided along outer surfaces of the storage nodes 12a and 12b; and capacitor electrode material 36 is provided over the capacitor dielectric material 34. The storage node 12a, together with the capacitor dielectric material 34 and the capacitor electrode material 36, forms a first capacitor 38a; and the storage node 12b, together with the capacitor dielectric material 34 and the capacitor electrode material 36, forms a second capacitor 38b. 
The capacitor electrode material 36 may be considered to form a plate electrode that extends across the capacitors 38a and 38b. The plate electrode is coupled with a reference voltage 40, which may be referred to as a common plate (CP) voltage. The CP voltage may be any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground≤CP≤VCC).
The capacitors 38a and 38b of FIG. 3 may be incorporated into a memory array. FIG. 4 schematically illustrates a prior art DRAM (dynamic random-access memory) array 42. The array includes a plurality of memory cells 44; with each memory cell including a transistor 28 and a capacitor 38. Wordlines (WL1, WL2 and WL3) extend along rows of the memory array, and bitlines (BL1, BL2 and BL3) extend along columns of the memory array. Each of the memory cells 44 is uniquely addressed through a combination of one of the wordlines with one of the bitlines.
The storage nodes 12a and 12b are shown in a desired configuration in FIG. 1; and the capacitors 38a and 38b are shown in a desired configuration in FIG. 3. However, a problem associated with the prior art configuration of FIG. 1 is that the storage nodes may shift from the desired configuration. FIG. 5 diagrammatically illustrates problematic shifting of the storage nodes, with solid lines indicating desired configurations of the storage nodes and dashed lines indicating shifted locations of the storage nodes. The lattices 18, 20 and 22 have failed to fully secure the storage nodes 12a and 12b; and accordingly the storage nodes may twist, bend, sway, etc., and thereby shift from the desired configuration. Arrows 46 are provided in FIG. 5 to emphasize the shifting of the storage node locations. The stresses along the various regions of the storage nodes 12a and 12b may be related to stresses of tall pillars, and in some cases may be described utilizing Euler's formula.
The shifting of the storage nodes 12a and 12b may detrimentally impact structural stability of the storage nodes, and may detrimentally impact structural stability of capacitors formed from such storage nodes. Such may lead to non-uniform performance across an array of capacitors, and may even result in inoperable devices.
It would be desirable to develop architectures which alleviate the problems described with reference to FIG. 5.